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`!Advanced Matrix Extensions`! (`!AMX`!), also known as `!Intel Advanced Matrix Extensions`! (`!Intel AMX`!), are extensions to the `F33f`_`[x86`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=X86]`_`f `F33f`_`[instruction set architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Instruction_set_architecture]`_`f (ISA) for `F33f`_`[microprocessors`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microprocessor]`_`f from `F33f`_`[Intel`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Intel]`_`f designed to work on `F33f`_`[matrices`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Matrix_(mathematics)]`_`f to accelerate `F33f`_`[artificial intelligence`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Artificial_intelligence]`_`f (AI) and `F33f`_`[machine learning`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Machine_learning]`_`f (ML) workloads.`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f]

>>Contents

• `F0af`_`[Extensions`#extensions]`_`f

• `F0af`_`[Tile matrix multiply unit`#tile-matrix-multiply-unit]`_`f

• `F0af`_`[Software support`#software-support]`_`f

• `F0af`_`[References`#references]`_`f

• `F0af`_`[External links`#external-links]`_`f

-─

>>Extensions

AMX was introduced by Intel in June 2020 and first supported by Intel with the `F33f`_`[Sapphire Rapids`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Sapphire_Rapids_(microprocessor)]`_`f `F33f`_`[microarchitecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microarchitecture]`_`f for `F33f`_`[Xeon`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Xeon]`_`f servers, released in January 2023. `:cite-ref-2[`F5bf`_`[2`#cite-note-2]`_`f] `:cite-ref-3[`F5bf`_`[3`#cite-note-3]`_`f] It introduced 2-dimensional `F33f`_`[registers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Processor_register]`_`f called tiles upon which accelerators can perform operations. It is intended as an extensible architecture; the first accelerator implemented is called tile matrix multiply unit (TMUL). `:cite-ref-iaiseaffpr-4-0[`F5bf`_`[4`#cite-note-iaiseaffpr-4]`_`f] `:cite-ref-5[`F5bf`_`[5`#cite-note-5]`_`f]

In Intel Architecture Instruction Set Extensions and Future Features revision 46, published in September 2022, a new AMX-FP16 extension was documented. This extension adds support for `F33f`_`[half-precision floating-point`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Half-precision_floating-point_format]`_`f numbers. In revision 48 from March 2023, AMX-COMPLEX was documented, adding support for half-precision floating-point `F33f`_`[complex numbers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Complex_numbers]`_`f. Both extensions are available in the `F33f`_`[Granite Rapids`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Granite_Rapids]`_`f set of server processors (with AMX-COMPLEX support only being available in `F33f`_`[Granite Rapids-D`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Xeon_D]`_`f `:cite-ref-6[`F5bf`_`[6`#cite-note-6]`_`f]).

>>>Tile matrix multiply unit

TMUL unit supports `F33f`_`[BF16`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bfloat16_floating-point_format]`_`f and `F33f`_`[INT8`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=INT8]`_`f input types. `:cite-ref-7[`F5bf`_`[7`#cite-note-7]`_`f] AMX-FP16 and AMX-COMPLEX also add support for real and complex `F33f`_`[FP16`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Half-precision_floating-point_format]`_`f numbers. The register file consists of 8 tiles, each with 16 rows of size of 64 bytes (32 BF16/FP16 or 64 INT8 elements). The only supported operation is matrix `F33f`_`[multiply and accumulate (MMA)`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Multiply–accumulate_operation]`_`f, which is the extension of the `F33f`_`[fused multiply–add (FMA)`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Fused_multiply–add]`_`f operation for scalar values as applied to matrix operands: `:cite-ref-8[`F5bf`_`[8`#cite-note-8]`_`f]

C n m = C n m + ∑ ∑ j = 1 J A n j B j m . {\\displaystyle C_{nm}=C_{nm}+\\sum _{j=1}^{J}A_{nj}B_{jm}.} `:cite-ref-iaiseaffpr-4-1[`F5bf`_`[4`#cite-note-iaiseaffpr-4]`_`f]

4th Gen Intel Xeon Scalable processor core can perform 2048 INT8 or 1024 BF16 operations per cycle: `:cite-ref-9[`F5bf`_`[9`#cite-note-9]`_`f] `:cite-ref-iaorm-10-0[`F5bf`_`[10`#cite-note-iaorm-10]`_`f] the maximal input sizes are 16 × × J {\\textstyle 16\\times J} for `*A`* and J × × 16 {\\textstyle J\\times 16} for `*B`*, where `*J`* is 64 for INT8 and 32 for BF16. The matrix multiplication requires 256 J {\\textstyle 256J} multiplication and 256 J {\\textstyle 256J} additions, thus performing 512 J {\\textstyle 512J} operations in 16 cycles.`:cite-ref-iaorm-10-1[`F5bf`_`[10`#cite-note-iaorm-10]`_`f]

>>Software support

• Compiler and assembler support

• `F33f`_`[LLVM`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=LLVM]`_`f 13`:cite-ref-11[`F5bf`_`[11`#cite-note-11]`_`f]`:cite-ref-12[`F5bf`_`[12`#cite-note-12]`_`f]`:cite-ref-13[`F5bf`_`[13`#cite-note-13]`_`f]`:cite-ref-0-14-0[`F5bf`_`[14`#cite-note-0-14]`_`f]

• `F33f`_`[GCC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GNU_Compiler_Collection]`_`f 11`:cite-ref-15[`F5bf`_`[15`#cite-note-15]`_`f]`:cite-ref-16[`F5bf`_`[16`#cite-note-16]`_`f]`:cite-ref-17[`F5bf`_`[17`#cite-note-17]`_`f]

• `F33f`_`[GNU Assembler`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GNU_Assembler]`_`f (GAS) initial support committed on 25 June 2020`:cite-ref-18[`F5bf`_`[18`#cite-note-18]`_`f]`:cite-ref-0-14-1[`F5bf`_`[14`#cite-note-0-14]`_`f]

• Operating system support

• `F33f`_`[glibc`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Glibc]`_`f support for detecting AMX feature in CPUs committed on 25 June 2020`:cite-ref-19[`F5bf`_`[19`#cite-note-19]`_`f]

• `F33f`_`[Linux kernel`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Linux_kernel]`_`f support since version 5.16`:cite-ref-20[`F5bf`_`[20`#cite-note-20]`_`f]

• `F33f`_`[VMware vSphere`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=VMware_vSphere]`_`f support for AMX in virtual machines released in `F33f`_`[ESXi`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ESXi]`_`f version 8.0u1 for VMs using Hardware Version 20`:cite-ref-21[`F5bf`_`[21`#cite-note-21]`_`f]

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f `:citerefhemsoth2021`aHemsoth, Nicole (August 19, 2021). "With AMX, Intel Adds AI/ML Sparkle to Sapphire Rapids". `*The Next Platform`*.

`:cite-note-2`!2.`! `F0af`_`[↑`#cite-ref-2]`_`f `:citerefonline2020`aonline, heise (28 June 2020). "Intel AMX: Erste Informationen zur Advanced Matrix Extensions Architecture". `*heise online`*.

`:cite-note-3`!3.`! `F0af`_`[↑`#cite-ref-3]`_`f `:citerefcutress`aCutress, Ian. "Intel Xeon Sapphire Rapids: How To Go Monolithic with Tiles". `*`F33f`_`[AnandTech`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AnandTech]`_`f`*. Archived from the original on August 31, 2021.

`:cite-note-iaiseaffpr-4`!4.`! `F0af`_`[↑`#cite-ref-iaiseaffpr-4-0]`_`f "Intel® Architecture Instruction Set Extensions and Future Features".

`:cite-note-5`!5.`! `F0af`_`[↑`#cite-ref-5]`_`f `:citerefschor2020`aSchor, David (June 29, 2020). "The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids".

`:cite-note-6`!6.`! `F0af`_`[↑`#cite-ref-6]`_`f `:citereflarabel2023`aLarabel, Michael (July 12, 2023). "Intel Granite Rapids D Support Merged Into GCC 14". `*`F33f`_`[Phoronix`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Phoronix_Test_Suite]`_`f`*.

`:cite-note-7`!7.`! `F0af`_`[↑`#cite-ref-7]`_`f "Advanced Matrix Extension (AMX) - x86 - WikiChip". `*en.wikichip.org`*.

`:cite-note-8`!8.`! `F0af`_`[↑`#cite-ref-8]`_`f "Generalized acceleration of matrix multiply accumulate operations". `*patents.google.com`*.

`:cite-note-9`!9.`! `F0af`_`[↑`#cite-ref-9]`_`f "Accelerate Artificial Intelligence (AI) Workloads with Intel Advanced Matrix Extensions (Intel AMX)" (PDF). Intel. Retrieved 2023-04-13.

`:cite-note-iaorm-10`!10.`! `F0af`_`[↑`#cite-ref-iaorm-10-0]`_`f "Intel® 64 and IA-32 Architectures Optimization Reference Manual Volume 1". Intel.

`:cite-note-11`!11.`! `F0af`_`[↑`#cite-ref-11]`_`f "What's New in LLVM for 4th Gen Intel® Xeon® & Max Series CPUs". Retrieved 21 April 2023.

`:cite-note-12`!12.`! `F0af`_`[↑`#cite-ref-12]`_`f `:citereflarabel2020`aLarabel, Michael (2020-07-02). "Intel AMX Support Begins Landing In LLVM". `*`F33f`_`[Phoronix`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Phoronix_Test_Suite]`_`f`*. Retrieved 2020-07-02.

`:cite-note-13`!13.`! `F0af`_`[↑`#cite-ref-13]`_`f "[X86-64] Support Intel AMX instructions". `*`F33f`_`[GitHub`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GitHub]`_`f`*. 2020-07-02. Retrieved 2020-07-02.

`:cite-note-0-14`!14.`! `F0af`_`[↑`#cite-ref-0-14-0]`_`f `:citereflarabel2020`aLarabel, Michael (2020-07-02). "Intel AMX Support Lands In The GNU Assembler". `*`F33f`_`[Phoronix`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Phoronix_Test_Suite]`_`f`*. Retrieved 2020-07-02.

`:cite-note-15`!15.`! `F0af`_`[↑`#cite-ref-15]`_`f "GCC 11 Release Series — Changes, New Features, and Fixes - GNU Project". Retrieved 21 April 2023.

`:cite-note-16`!16.`! `F0af`_`[↑`#cite-ref-16]`_`f "[PATCH] Enable GCC support for AMX". 2020-07-06. Retrieved 2020-07-09.

`:cite-note-17`!17.`! `F0af`_`[↑`#cite-ref-17]`_`f "Enable GCC support for AMX-TILE, AMX-INT8, AMX-BF16. · gcc-mirror/gcc@5c60984". `*GitHub`*. Retrieved 2022-09-05.

`:cite-note-18`!18.`! `F0af`_`[↑`#cite-ref-18]`_`f "commits with Intel AMX". 2020-07-02. Retrieved 2020-07-02.

`:cite-note-19`!19.`! `F0af`_`[↑`#cite-ref-19]`_`f "x86: Detect Intel Advanced Matrix Extensions". 2020-07-02. Retrieved 2020-07-02.

`:cite-note-20`!20.`! `F0af`_`[↑`#cite-ref-20]`_`f "Linux 5.16 Features Include FUTEX2, Intel AMX, Folios, DG2/Alchemist, More Apple Silicon Support". `*`F33f`_`[Phoronix`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Phoronix_Test_Suite]`_`f`*.

`:cite-note-21`!21.`! `F0af`_`[↑`#cite-ref-21]`_`f "Accessing Sapphire Rapids AMX instructions on vSphere". `*Earl C. Ruby III`*. 2023-08-24.

>>External links

• Intel Intrinsics Guide

• Wikichip: Advanced Matrix Extension (AMX) - x86

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